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stnolting/neorv32: :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
RISC-V 指令集架構介紹 - Integer Calling convention | Jim's Dev Blog
riscv-collab/riscv-gnu-toolchain: GNU toolchain for RISC-V, including GCC
syntacore/scr1: SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Qualcomm—one of Arm’s biggest customers—starts a RISC-V joint venture | Ars Technica
[https://arstechnica.com/gadgets/2023/08/qualcomm-one-of-arms-biggest-customers-starts-a-risc-v-joint-venture/] - - public:mzimmerm
European Processor Initiative Receives First EPAC RISC-V Sample Chips for Testing | Tom's Hardware
Reddit - RISCV - How to install risc- v emulator?
[https://amp.reddit.com/r/RISCV/comments/mjuc2p/how_to_install_risc_v_emulator/] - - public:mzimmerm
run riscv interpreter in docker
RISC-V Interpreter
[https://www.cs.cornell.edu/courses/cs3410/2019sp/riscv/interpreter/] - - public:mzimmerm
execute riscv instructions