syntacore/scr1: SCR1 is a high-quality open-source RISC-V MCU core in Verilog [https://github.com/syntacore/scr1] - 2023-11-30 03:54:06 - public:speqz core, riscv - 2 | id:1485393 -
EEMBC -- The Embedded Microprocessor Benchmark Consortium [http://www.eembc.org/coremark/] - 2013-11-22 09:39:31 - public:speqz arm, core, cpu, embedded, mips - 5 | id:251891 -